1. Field of the Invention
The present invention relates to a parallel processor, and more particularly to a parallel processor suitably used for a graphic job.
2. Background Art
Hitherto, there is a processor system in which a plurality of processors each of which includes, for example, a CPU and a local memory are connected to a common bus, wherein a CPU in a certain processor performs writing and reading a local memory in one of the other processors through the common bus.
Another system is known which includes a plurality of common buses and transference of data between processors are individually performed. A still further known system is arranged such that a plurality of processors are connected annularly, in the form of a lattice, or a binary tree. In addition, a system is known which is arranged in such a manner that communication is performed between processors connected vertically and laterally, that is so-called "a CAP (Cellular Array Processor)" is formed.
However, in any one of the above-described processor systems, the connection established between processors is fixed. Therefore, although specific processings can be performed at high speed, a problem arises in that it is difficult for the systems to correspond to the change in the algorithm, causing their use to be limited.
To this end, an object of the present invention is to provide a parallel processor in which the connections between a plurality of processors can be re-structured in accordance with the processing algorithm and various processings can be performed at high speed by means of a parallel operation.